Pseudorandom BIST: Theory, Simulation and Tester Data

We present experimental results from the Murphy and ELF35 test chip experiments to try to answer the following questions related to pseudo-random BIST: (1) How effective is the probability model relating test escape probability and test length of pseudo-random patterns? (2) How effective is the single stuck-at fault model used in predicting escape probability when pseudo-random patterns of a given test length are applied? (3) How effective are the defect-level prediction models? (4) How effective is mapping logic? Our data show that: (1) Fault simulation results and [McCluskey 88] give very close results. (2) McCluskey-Buelow model gives a conservative estimation for the test length to achieve a given defect level. (3) Mapping logic is effective in detecting defective chips with shorter test length than pure pseudorandom BIST. * Chao-Wen Tseng is currently with Zettacom and Stanford CRC § James Li is currently with National Taiwan University ‡ Subhasish Mitra is currently with Intel